1. Field of the Invention
The present invention relates to electronic circuits that will convert a master clock signal to other timing signals. More particularly, the present invention relates to electronic circuits that will convert a master clock signal to timing signals having a frequency that is a multiple of the master clock frequency and has programmable placement of the rising and falling edges of the timing signals.
2. Description of Related Art
Clock synthesizers are well known in the art for generation of timing signals in electronic systems. A master clock or fundamental clock will be distributed within an electronic system. The master clock will then be multiplied by a factor to form a group of timing signals within a functional unit such as an integrated circuit. Often individual timing signals will have a requirement that the transition from a logical 0 to a logical 1 (a rising edge) or the transition from a logical 1 to a logical 0 (a falling edge) be located in time relative to the rising or falling edge of the master clock or to another of timing signal.
Microprocessors, for example often have two or more clock phases distributed within the circuitry of the microprocessor. A circuit such as a phase lock loop or delay locked loop is used to create the timing signals that are multiplied from the master clock. Delay or phase shift circuits will adjust the rising edge and falling edges relative to each other.
Phase locked loops and delay locked loops have notoriously long lock times to synchronize the master clock with the timing signals. Thus, if any of the timing signals need to be adjusted during operation, any programming of the timing circuits would introduce an inordinate latency to the changes. Further, any changes in latency would require increasing the complexity of the delay circuits, thus increasing any inherent error in the system.
U.S. Pat. No. 5,687,202 (Eitrheim) discloses a programmable phase shift clock generator having a phase comparator for generating a difference between an input clock signal and a feedback signal an up-down counter responsive to the phase comparator, for generating an n-bit count, a ring oscillator responsive to the up-down counter, for generating a loop clock signal as an output and as feedback to the phase comparator, and an adjustable delay line to provide a phase shifted clock signal from the loop clock output signal. A feature of Eitrheim is providing a digital signature of an input clock for further utilization in generating ancillary clock signals. A second feature is the ability to adjust precisely the duty cycle of an output clock independent of the input clock frequency.
U.S. Pat. No. 5,444,405 (Truong et al.) describes a system and method for providing programmable non-overlapping clock generation on a chip. The invention includes four main embodiments. The first embodiment is directed to the overall operation of an on-chip clock generator. The second embodiment is directed to a hardware programmable clock generation system and method. The third embodiment is directed to a software programmable clock generation system and method. The fourth embodiment is directed to a combination of all three embodiments.
The programmable on-chip clock generator provides two phases of a system clock with non-overlapping edges. The programmability of the clock generator provides flexibility during chip fabrication, and during functioning in an operational environment.
During the manufacturing phases of chip production, characteristics of the on-chip clock generator are altered to ensure the edges of the two generated clock do not overlap. This allows the manufacturer to optimize the performance of the chip, while the chip is undergoing initial production testing. This feature obviates the need to perform costly and time consuming trial-and-error design and redesign of on-chip clock generators.
Additionally, Truong et al. provides a technique for optimizing the performance of the on-chip clock generator after the chips have left the manufacturing environment. One feature of Truong et al. is the ability to adjust clock generation dynamically to account for climatic changes in an operational, or other post-production, environment. This allows chips to be manufactured with wider tolerances and allows operation of the chip to be optimized when the chip is in the operational environment. Adjustments to the on-chip clock generator during the manufacturing phase are referred to as hardware programming because the manufacturer alters the physical composition of the clock generator. Adjustments to the on-chip clock generator once the chip is fabricated and in the operational environment are referred to as software programming. This terminology reflects the fact that using software commands, the characteristics of the on-chip clock generator can be adjusted to compensate for changes in the operating environment. Programming capability in both cases is accomplished by adding or subtracting delay elements in feedback paths within the clock generator circuit.